1. Field of the Invention
The present invention relates to a variable threshold voltage complementary MOSFET with a SOI structure.
2. Description of the Related Art
LSIs of low electric power and high performance are important as key devices for next-generation products of personal and mobile communications. When an LSI is configured with the use of a bulk Si CMOSFET having a typical silicon substrate, the power consumption of the LSI is increased because of the realization of high integration and high speed with the miniaturization of the LSI. Therefore, a low electric power MOSFET having a new device structure that can form an LSI of low electric power and high performance is eagerly waited. In this situation, a fully depleted SOI CMOS (CMOS: Complementary MOSFET) fabricated with the use of a SOI (Silicon on Insulator) substrate having an insulating layer between a support substrate and a silicon layer (device region) is expected as a device of low electric power and high speed. Since a buried oxide film exists under the silicon layer as the insulating layer in the SOI MOSFET, a parasitic capacitance between the source and drain is reduced to allow operations at low electric power and high speed. Furthermore, since the buried oxide film completely separates devices from each other, there are advantages that latch up is not generated and high-density layout is possible. Moreover, in the fully depleted SOI MOSFET, a gradient of drain current can be increased against gate voltage in the subthreshold region of the MOSFET as compared with the bulk Si MOSFET. Therefore, there is an advantage that this difference in the same OFF-current effectively serves to improve performance at low voltage.
As described above, the fully depleted SOI MOSFET has many advantages. In addition to this, it is known that Vth can be varied by applying bias voltage to the support substrate in the relationship of|ΔVth|=γ|ΔVbs|because the entire silicon layer in the channel part is depleted. (For example, see Non-patent Document 1 and Non-patent Document 2.) Where Vth is the threshold voltage of the fully depleted SOI MOSFET, Vbs is adjusted bias voltage for adjusting the threshold voltage, and γ is a substrate bias coefficient of the SOI substrate.
A device of a variable threshold voltage SOI MOSFET utilizing the properties described above will be described with reference to drawings. FIG. 6 is a cross-sectional view schematically illustrating the structure of the essential part of a variable threshold voltage SOI MOSFET. This variable threshold voltage SOI MOSFET is the fully depleted SOI MOSFET in which a depletion layer is spread throughout a channel part. The variable threshold voltage SOI MOSFET has a silicon layer 29, that is, a SOI layer, on a support substrate 10 through an insulating layer 20. In the silicon layer 29, a source region 32 and a drain region 34 are formed as they sandwich a channel part 36. A source electrode 44 and a drain electrode 46 are disposed so as to contact with the source region 32 and the drain region 34, respectively. A gate electrode 53 is disposed on the channel part 36 as they sandwich a gate insulating film 52. An adjusted bias electrode 63 for applying the adjusted bias voltage Vbs to adjust the threshold voltage of the MOSFET is disposed on the support substrate 10.
FIG. 7 is a diagram for illustrating the operation of an N-channel variable threshold voltage SOI MOSFET where a source region 32 and a drain region 34 are N-type semiconductors. The horizontal axis is gate voltage Vg, and the vertical axis is drain current Id (positive value) by log scale. Vd is power supply voltage. By varying the adjusted bias voltage Vbs, a standby state that the adjusted bias voltage Vbs is 0 V (indicated by Curve I in FIG. 7) is switched to an active state that a positive adjusted bias voltage Vbs is applied (indicated by Curve II in FIG. 7), for example. Moreover, in FIG. 7, Ion1 and Ion2 indicate ON-currents in the standby state and the active state, respectively, and Ioff1 and Ioff2 indicate OFF-currents in the standby state and the active state, respectively. Since the OFF-current is suppressed in the standby state (in a stat of Ioff1<Ioff2), the power consumption is reduced. In the meantime, since the ON-current is increased in the active state (in a state of Ion2>Ion1), high-speed operations are feasible. A variable threshold voltage CMOS utilizing these properties is proposed.
A traditional example of the variable threshold voltage CMOS will be described with reference to FIG. 8. The variable threshold voltage CMOS is configured by combining an N-channel MOSFET with a P-channel MOSFET. More specifically, first and second MOSFETs 12 and 14 are separately formed on an insulating layer 20 of a layered product 25 as the MOSFETs share the layered product 25 formed of a support substrate 10 and the insulating layer 20 disposed on one surface of the support substrate 10. The first MOSFET 12 is the N-channel type, and the second MOSFET 14 is the P-channel type.
In the variable threshold voltage CMOS, the first MOSFET 12 has a first source region 31, a first drain region 33, a first channel part 35 sandwiched between the both regions 31 and 33, and a gate electrode 55 disposed on the channel part 35 as they sandwich a gate insulating film 54 in a silicon layer formed on the insulating layer 20. In the drawing, 45 and 47 are a source electrode and a drain electrode, respectively.
Similarly, the second MOSFET 14 has a second source region 37, a second drain region 39, a second channel part 42 sandwiched between the both regions 37 and 39, and a gate electrode 61 disposed on the channel part 42 as they sandwich a gate insulating film 60 in a silicon layer formed on the insulating layer 20. In the drawing, 49 and 51 are a source electrode and a drain electrode, respectively.
In addition, on the surface opposite to the insulating layer of the support substrate 10 (backside), an adjusted bias electrode 63 to which the adjusted bias voltage Vbs is applied is disposed as shared by the first and second MOSFETs 12 and 14 as similarly described with reference to FIG. 6.
Here, the first channel part 35 and the second channel part 42 are thoroughly depleted, and the first MOSFET 12 and the second MOSFET 14 are the fully depleted SOI MOSFETs.
In this configuration, the adjusted bias voltage Vbs is applied to the adjusted bias electrode 63 disposed on the support substrate 10, which causes the threshold voltages of the first MOSFET 12 and the second MOSFET 14 to be varied.
Non-patent Document 1
Nagumo et al. Sikii-den'atu kahen-gata kanzen kubou-gata SOI MOSFET no sikii-den'atu tyousei han'i, Technical Report of IEICE. SDM 2002-138, ICD 2002-49 (2002-08) P. 20
Non-patent Document 2
T. Hiramoto et al. Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS), Jpn. J. Appl. Phys. Vol. 40 (2001) pp. 2854 to 2855
However, the P-channel variable threshold voltage SOI MOSFET operates in opposite ways to the response of the threshold voltage of the N-channel variable threshold voltage SOI MOSFET.
The manner that the P-channel variable threshold voltage SOI MOSFET operates in opposite ways will be described with reference to FIG. 9. The horizontal axis indicates gate voltage Vg, and the vertical axis indicates drain current Id by log scale. In the P-channel MOSFET, the drain current Id is a negative value, thus indicated by the absolute value. Vd is power supply voltage. By varying the adjusted bias voltage Vbs, a standby state that the adjusted bias voltage Vbs is 0 V (indicated by Curve IV in FIG. 9) is switched to an active state that the positive adjusted bias voltage Vbs is applied (indicated by Curve III in FIG. 9), for example. Furthermore, in FIG. 9, Ion3 and Ion4 indicate ON-currents in the active state and the standby state, respectively, and Ioff3 and Ioff4 indicate OFF-currents in the active state and the standby state, respectively. The OFF-current is suppressed in the active state (the state of Ioff3<Ioff4), whereas the ON-current is increased in the standby state (the state of Ion4>Ion3).
On this account, in the case where the adjusted bias voltage Vbs is applied to the support substrate 10 for adjusting the threshold voltage in the variable threshold voltage CMOS having the structure shown in FIG. 8, the threshold voltage is reduced in the N-channel MOSFET 12, for example, and then the threshold voltage is increased in the P-channel MOSFET 14. Therefore, when the adjusted bias voltage Vbs is simply applied to the support substrate 10, the ON-current of the N-channel MOSFET 12 is increased, and then the ON-current of the P-channel MOSFET 14 is reduced.
When the variable threshold voltage CMOS combining the P-channel MOSFET with the N-channel MOSFET in which the MOSFETS operate in opposite ways is incorporated in a current mirror type circuit, for example, it is unlikely to expect improved properties of the current mirror circuit as desired.
For the scheme to solve this, a scheme can be considered that the adjusted bias voltage Vbs is separately applied to each region. However, when an electrode for applying the adjusted bias voltage Vbs to each region is separately formed, a disadvantage is generated such as complicated fabrication processes.
Then, as a result of various investigations done by the inventor of this application, a conclusion is obtained. A CMOS structure is formed in which a so-called partially depleted MOSFET where a depletion layer is not spread to the under area of a channel part and a fully depleted MOSFET are separately formed on a shared layered product formed of a support substrate and an insulating layer formed thereon. Therefore, the threshold voltage of the fully depleted MOSFET can be varied when the common adjusted bias voltage Vbs is applied from the support substrate side, whereas the threshold voltage of the partially depleted MOSFET can be kept at fixed voltage, not allowed to change the set threshold voltage.